1. Field of the Invention
The present invention relates generally to the field of mixed-signal systems-on-chip (SoC) and more particularly, to the reduction of noise at sampling times of analog circuits in mixed-signal SoCs.
2. Description of the Prior Art
With the advent of the digital age, technology has rapidly advanced in recent decades. Such advancements have resulted in combining analog and digital circuitry in mixed-signal systems-on-chips (SoCs) integrating analog and digital circuits onto a common substrate of a chip (or integrated circuit).
Analog circuits typically exhibit high levels of sensitivity to noise. On the other hand, digital blocks can induce significant amount of disturbance and adversely impact the performance of neighboring analog circuits. In certain designs of SoCs, for example, an analog-to-digital converter (ADC) may be placed next to a digital signal processor (DSP). The ADC converts signals that are in analog form to digital form. In so doing, the ADC samples the analog signal at predetermined time periods (sampling times) to generate the digital signal. It is important to minimize or even eliminate the amount of disturbance generated by the DSP at sampling time when an ADC and DSP residing on the same substrate. Otherwise, key performance characteristics of the ADC, such as signal-to-noise ratio (SNR), is substantially degraded. This is perhaps better understood with reference to a figure.
FIG. 1 shows a timing diagram of clocks generated (clocking scheme) using prior art techniques. The clock signals in FIG. 1, CLK1X, CLK2X, and CLK4X, are applied to the DSP (or digital circuit) and trigger its activities. The clock signal, CLK1X, has the same frequency or period as that of the ADC clock reflected by the clock signal CLK_ADC. It is well known that digital circuits typically employ the edge of a clock to synchronize, sample digital signals, or trigger certain activities. Accordingly, as shown in FIG. 1 using the dashed line, the digital activity spikes at the rising and falling edges of the signal CLK1X.
In FIG. 1, the clock signal, CLK2X, has a frequency twice that of the signal CLK1X and the signal, CLK4X, has a frequency twice that of the CLK2X. At the edges of all of these clock signals, the activity of the digital circuit (DSP in this case) that resides on the same substrate as that of the analog or ADC peaks and tapers off within half of a period. As earlier noted, in FIG. 1, corresponding digital activities/disturbances generated by each of the clock signals, CLK1X, CLK2X and CLK4X, are drawn as dashed lines. However, the tapering off of activity of the DSP circuit barely occurs before the analog signal is sampled by the ADC (at the rising edge of the clock signal CLK_ADC). That is, the time from the completion of the DSP activity (disturbance climaxes) and the ADC sampling time, tQuiet (also known as temporal gap or the quit zone) is undesirably small, which leads to noise on the signal CLK_ADC and therefore unreliable sampling.
Therefore, the need arises for analog circuits having enhanced noise immunity from digital circuits sharing a common substrate on a chip or integrated circuit.